What is Wafer Grinding/Thinning What is Wafer Grinding/Thinning What is Wafer Grinding/Thinning

What is Wafer Grinding/Thinning?

Wafer backgrinding, also known as Wafer thinning, is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density packaging of integrated circuits (IC).

ICs are being produced on semiconductor wafers that undergo a multitude of processing steps. Silicon wafers commonly used today are roughly 750 μm thick to ensure a maximum of mechanical stability and to avoid warping during high-temperature processing steps.

Smartcards, USB memory sticks, smartphones, handheld music players, and other ultra compact electronic products would not be feasible in their present form without minimizing the size of their various components along all dimensions. The backside of the wafers are thus “ground” or “thinned” prior to wafer dicing (where the individual microchips are being singulated). Wafers thinned down to 75 to 50 μm are common today.

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Axus Partners with CP Display to Accelerate Monolithic 1080p MicroLED Displays to Mainstream AR

Axus partners with Compound Photonics US Corporation to accelerate sub 5 µm pixel microLED development to the mass market.

Axus and CP are partnering to integrate critical wafer-scale processes needed for mass-production scale up of CP’s 3 µm pixel, 0.26” diagonal, 1080p microLED displays for the next generation AR glasses. Specifically, Axus will deploy its state-of-the-art Capstone CMP system with integrated post-CMP clean to enable wafer planarization and surface preparation process solutions for successful wafer-scale bonding of microLED wafers to high-performance CMOS backplanes.

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Axus/Plessey Partnership

Axus partners with Plessey Semiconductors to help bring high-performance GaN-on-Silicon monolithic microLED technology to the mass market.

Using tooling from Axus and optimised processes, Plessey Semiconductors has achieved a successful wafer to wafer bond of a 1080p microLED display 0.26” diagonal to a 3-micron pixel-pitch backplane. Much smaller than the 0.7" diagonal 8-micron pixel-pitch active-matrix display previously demonstrated.

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