The Process Development Lab & Foundry Services team is composed of a prestigious group of process and tool engineers along with wafer metrology experts. We help clients identify their chemical mechanical polishing (CMP) needs and work with them to custom design and develop the CMP process and advanced wafer solutions that fits their needs to build the device of the future.
In need of SiC Processing? Axus Technology’s has been working diligently to develop and improve leading-edge CMP process performance and hardware capability for advanced single-wafer silicon carbide (SiC) CMP applications. The primary focus of these efforts include: 1) thin/fragile wafer handling reliability, 2) premium substrate flatness (TTV), 3) substrate surface quality, and 4) reduced cost of ownership (CoO).
Based on the architecture of the state-of-the-art Capstone® CMP system, coupled with our Crystal carrier specifically designed for fragile wafer handling and advanced profile control, Axus has achieved and demonstrated process performance that has so far met or exceeded all customer specifications.
Axus has successfully handled and processed 150mm diameter SiC substrates from SEMI-standard thickness of 350 microns down to 175 microns, without the need for temporary bonding or handle wafers to support these substrates, as shown in Figure 1 below.
As also shown in Figure 1, in addition to fragile wafer handling capability, Crystal carriers also provide the ability to accurately control the material removal profile during CMP, thus allowing customers to reduce pre-CMP TTV and produce premium quality, sub-micron TTV substrates. The market demand for such substrates will continue to drive the high end of SiC wafer pricing and supplier profit margins.
In other cases, Axus has demonstrated the ability to reduce substrate TTV by several microns during full CMP processing (Si-face and C-face) during customer process demonstrations.
For surface quality optimization, Axus works closely on both CMP consumables development and process optimization on Capstone®. These efforts have resulted in the ability to generate sub-Angstrom (Ra) surface finish with a single-step process, see Figure 2 below.
Capstone® is the only advanced CMP tool in the market that supports both single-wafer and dual-wafer processing. Dual-wafer processing has been demonstrated to reduce CMP consumables CoO by as much as 50% as compared to current processes of record used on more mature CMP tools.
Since reducing SiC CMP CoO requires faster removal rates and corresponding process throughput, SiC CMP processes typically run at higher wafer pressures and rotation speeds, also known as PV value (pressure x velocity) compared to other, more mature CMP applications such as silicon. Process temperature becomes a limiting factor as the PV value increases.
Axus has developed a proprietary process cooling system that enables high PV value CMP processes that substantially increase the material removal rate without exceeding the maximum temperature limits of other components of the CMP process, particular the polishing pad. See Figure 3 below.
Process temperature control further enables dual-wafer processing for managing the process temperature in both single-wafer and dual-wafer process scenarios. Based on the Capstone® architecture, both platens can perform dual-wafer processing simultaneously, resulting in parallel processing of four wafers concurrently. Capstone® is the only advanced CMP tool on the market that can process this many wafers in parallel, further improving its throughput advantage.
Recent process improvements have yielded a material removal rate above 10 microns per hour on the silicon face. As a major industry breakthrough for Advanced Single-Wafer Silicon Carbide CMP, Axus Technology is providing SiC wafer suppliers with the most advanced CMP system on the market and unmatched performance benefits. The state-of-the-art Capstone® CMP system, coupled with our Crystal carrier (specifically designed for fragile wafer handling and advanced profile control), delivers premium-quality SiC substrates with sub-micron TTV and sub-Angstrom surface finish. The net result for Capstone® users is higher throughput while reducing consumables usage and cost of ownership (CoO) significantly.