Edge grinding, also known as Edge Profiling, is a process that is common to the manufacture of nearly all semiconductor related wafers and wafers that are used in the manufacture of many other electronic, solar, and nanotechnology devices.
The edge grinding step is critical to the safety of the wafer edge. Silicon in it’s crystalline state is very brittle and if the edge is not profiled or rounded off, it will flake during handling and certainly during follow-on processing steps both mechanical in nature and thermally dynamic in nature. Edge flaking is not only catastrophic for the individual wafer it can be a disaster for other wafers that are being processed if the edge flake contaminates the processing equipment or nearby wafers.
What has become generally known as the “bullet nose” shape and variations of this shape are the most common for monocrystalline silicon wafers of all sizes in the semiconductor industry. The shape of the “nose” may be blunter if the wafers are to be processed farther down the line using the CMP process, or they may be more aerodynamic if the wafers are not going to go through a CMP process. This is because a blunter shape will help hold the wafers more securely within the template seat or the retaining ring of the wafer carrier during the CMP process.
In certain applications that require the use of ultra-hard and brittle substrates of Silicon Carbide, Sapphire, or GaN materials, such as those associated with the manufacture of Light Emitting Diodes (LEDs), a different type of edge treatment is sometimes deemed
appropriate. This type of edge treatment is often called a “Bevel Nose.” Due to the importance of the critical crystal plane orientation, a rounded edge profile is not used for typical hard, brittle LED substrate materials.
More information and a full description of the Edge Grinding process employed at Axus Technology can be found in our Edge Grinding Application Note.
It takes excellent, well-trained personnel plus the right equipment and tooling to do the Edge Grinding process well enough to meet SEMI specifications. Years of experience gained in the actual processing of wafers of many types of materials helps Axus Technology to have the skill set necessary to perform at this level. We meet and often exceed customer expectations for Edge Grinding because of our unique perspective; some of our people have actually been a part of the design teams during the engineering and manufacturing phases of the development of this type of processing equipment.
FOR PROCESS SERVICES: If you are looking for a partner company to perform Edge Grinding and Edge Profiling on a contractual basis on your wafer substrates, our Process Services Department is ready to discuss this with you.
FOR EQUIPMENT AND TOOLING: If you are planning to perform this process in-house in your own facilities, we can help with your equipment choice by offering to you a selection of refurbished Edge Grinding equipment and tooling including the appropriate diamond wheels to perform this critical process step with accuracy, repeatability, and dependability.
Please contact Axus Technology and learn more about this and our many other polishing, grinding, and cleaning process capabilities
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Axus Partners with CP Display to Accelerate Monolithic 1080p MicroLED Displays to Mainstream AR
Axus partners with Compound Photonics US Corporation to accelerate sub 5 µm pixel microLED development to the mass market.
Axus and CP are partnering to integrate critical wafer-scale processes needed for mass-production scale up of CP’s 3 µm pixel, 0.26” diagonal, 1080p microLED displays for the next generation AR glasses. Specifically, Axus will deploy its state-of-the-art Capstone CMP system with integrated post-CMP clean to enable wafer planarization and surface preparation process solutions for successful wafer-scale bonding of microLED wafers to high-performance CMOS backplanes.
Axus partners with Plessey Semiconductors to help bring high-performance GaN-on-Silicon monolithic microLED technology to the mass market.
Using tooling from Axus and optimised processes, Plessey Semiconductors has achieved a successful wafer to wafer bond of a 1080p microLED display 0.26” diagonal to a 3-micron pixel-pitch backplane. Much smaller than the 0.7" diagonal 8-micron pixel-pitch active-matrix display previously demonstrated.