SiC PROCESSING

Axus Technology has been working diligently to develop and improve leading-edge CMP process performance and hardware capability for advanced single-wafer silicon carbide (SiC) CMP applica-tions. The primary focus of these efforts include: 1) thin/fragile wafer handling reliability, 2) premium substrate flatness (TTV), 3) substrate surface quality, and 4) reduced cost of ownership (CoO).

Based on the architecture of the state-of-the-art Capstone® CMP system, coupled with our Crystal carrier specifically designed for fragile wafer handling and advanced profile control, Axus has achieved and demonstrated process performance that has so far met or exceeded all customer spec-ifications.
Axus has successfully handled and processed 150mm diameter SiC substrates from SEMI-standard thickness of 350 microns down to 175 microns, without the need for temporary bonding or handle wafers to support these substrates, as shown in Figure 1 below.

As shown in Figure 1, in addition to fragile wafer handling capability, Crystal carriers also provide the ability to accurately control the material removal profile during CMP, thus allowing customers to reduce pre-CMP TTV and produce premium quality, sub-micron TTV substrates. The market demand for such substrates will continue to drive the high end of SiC wafer pricing and supplier profit mar-gins.

In other cases, Axus has demonstrated the ability to reduce substrate TTV by several microns during full CMP processing (Si-face and C-face) during customer process demonstrations.

For surface quality optimization, Axus works closely on both CMP consumables development and process optimization on Capstone. These efforts have resulted in the ability to generate sub-Ang-strom (Ra) surface finish with a single-step process, see Figure 2 below.