Axus Technology Offers CMP Foundry Services and Equipment
The Axus Technology engineering team provides advanced technical solutions for CMP process services ranging from advanced CMP process development to standard production CMP foundry services. With a fully equipped Class 100 cleanroom staffed by engineers with decades of semiconductor process experience, Axus is ready to assist you with all your CMP process needs.
Axus is also a worldwide seller and distributer of remanufactured CMP tools such as Applied Material’s Mirra and Mirra Mesa, IPEC, Speedfam and Strasbaugh CMP systems, new G&P Technology CMP tools, tool upgrades, tool parts, and tool maintenance services.
What is Chemical Mechanical Planarization/Polishing (CMP)?
Over the decades that solid-state devices have been created in Silicon substrates, the processes to create the substrates have utilized polishing to create a surface with extremely good flatness and roughness. In this polishing process the wafer surface is being acted upon by a slurry and a polishing pad. The slurry is most commonly an aqueous mixture that includes sub-micron abrasive particles and chemistry. A force is applied to the wafer to press it into the pad and both have motion to create a relative velocity. The motion and force leads to portions of the pad creating abrasion by pushing the abrasive against the substrate while it moves across the wafer surface. The chemistry added to the slurry alters the material being polished on the surface of the wafer. This mechanical effect of abrasion combined with chemical alteration is called Chemical Mechanical Planarization or Polishing (CMP). The removal rate of the material can be easily an order of magnitude higher with both the chemical and mechanical effects simultaneously compared to either one taken alone. Similarly, the smoothness of the surface after polishing is also optimized by using chemical and mechanical effects together.
What is CMP used for now?
In the 1980’s, the Semiconductor industry was struggling with the dimensional scaling dictated by Moore’s law. Shrinking the dimensions of the transistor devices created a need for more layers of wiring to hook them all up. Each time a layer of dielectric or metal was deposited and a pattern etched in it, more topography was created on the wafer surface. The topography interfered with the ability to perform the lithography for the next pattern. Chemical Mechanical Planarization (also CMP) was born by applying the principles of Chemical Mechanical Polishing to processes that flattened or planarized the topography in the dielectric surface prior to patterning.
Soon after that, the CMP processes being applied to dielectric films were also applied to conductor films such as Tungsten, Titanium, and doped polysilicon as well. Troughs are etched into the planarized dielectric. Those troughs ware overfilled with metal and then the excess metal is removed with CMP processes to leave metal only in the trough. The planar patterns created with these processes have enabled high yield ever since for interconnect wiring with a rising number of layers. From those beginnings, there has been an explosion in the number of CMP process applications. Those were mostly for new wiring structures and materials at first. In moving to Copper, the oxide CMP and Tungsten CMP processes were replaced by Copper CMP and Tantalum barrier CMP. More recently, the use of CMP has been climbing for the creation of new structures and materials in device fabrication. Shallow Trench Isolation (STI) CMP was for a long time the only type of CMP in the Front End. Now the transition to transistors with metal gates requires an extra dielectric CMP process and an extra metal CMP process. The move beyond standard 2-dimensional transistors will continue this trend of additional CMP steps.
Other parts of the electronics industry have seen what CMP can do and are taking full advantage, too. CMP applications now include special processes for creating hard disk drives and the read-write heads that go with them. Some of aspects of CMP for wafers have been applied to making glass panels and optical components. There has also been a rapid expansion of CMP for 3DIC and wafer-scale packaging as well as alternative substrate for a wide variety of uses including LED lighting.
How is it done?
The largest suppliers of CMP process equipment today are Applied Materials and Ebara. The tools that they sell today have 2, 3, or 4 turning tables, called platens, on which the pads are mounted. This enables multi-step CMP processes to occur in a single tool. The wafer is brought from the cassette to a load station where it is temporarily attached to a wafer carrier or polishing head using vacuum to pick it up with the side of the wafer to be polished is facing down. During the polishing, the carrier comes down on one side of the pad and both the carrier and platen spin the same direction. This is a good way of creating a fairly uniform relative velocity between the wafer and the pad in a compact space. Today’s advanced heads are capable of pre-compressing the pad and various degrees of radial control of downforce pressure for tailoring of removal rate across the wafer as needed. The slurry is sent onto the pad surface near the center of the pad in a controlled quantity. Through centrifugal force, it moves toward the wafer and then off the edge of the pad for disposal.
In today’s CMP process tools, after the last polishing step is completed, the wafer is sent to the cleaning portion of the tool. Great care is taken to remove the particles that are introduced in the polishing. Common elements of these systems are brush boxes for double-sided scrubbing of the wafer with brushes made from PVA foam. Another common element in a spin box where the wafer is spun at high RPM’s for rinsing and then drying. A large installed base also exists of polishers with names like IPEC, Speedfam, and Strasbaugh that send the wafer to a wet cassette after polishing. The wet cassette is then placed into a standalone cleaner with a name like OnTrak or DNS.
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Axus partners with Plessey Semiconductors to help bring high-performance GaN-on-Silicon monolithic microLED technology to the mass market.
Using tooling from Axus and optimised processes, Plessey Semiconductors has achieved a successful wafer to wafer bond of a 1080p microLED display 0.26” diagonal to a 3-micron pixel-pitch backplane. Much smaller than the 0.7" diagonal 8-micron pixel-pitch active-matrix display previously demonstrated.