Escalating production of silicon carbide (SiC) semiconductors has driven process technology to innovate at a rapid pace to overcome specific challenges and make the most of the material’s advantages. The primary areas of improvement in SiC materials have been heightened crystal quality, reduced defectivity and better yields. More relevant to CMP are improvements such as reduced stress, which affects wafer shape – bow and warp primarily – which can lead to significant wafer handling and processing challenges.
These advancements all have a significant impact on the economics of SiC production. Yield is a major economic driver for all semiconductor-related commercial considerations, and this is truer for SiC than it is for nearly any other material or technology we’ve seen before.
Advancements in SiC technology and chemical-mechanical planarization (CMP) processes lead to better wafer quality, which drives higher yields, while cost of ownership (CoO) and productivity improvements propel lower manufacturing costs. In turn, this expands market adoption, significantly impacting such key SiC end applications as electric vehicles, renewable energy, and high-power electronics.
CMP for SiC: Challenges, benefits and evolution
CMP processing for SiC device wafers is far more challenging than for silicon. This can be attributed to the host of factors associated with the properties of the material itself, which is far more complex than standard silicon. Chief among these factors are:
- High fragility – SiC wafers are very brittle, requiring the use of specialized wafer carriers and handlers to minimize the risk of breaking or damage
- High hardness – close to that of diamonds, SiC wafer hardness requires much longer processing times and much more aggressive process conditions and chemistry to enable efficient processing
- Transparent – with their wide bandgap, SiC wafers are highly transparent, unlike silicon wafers, which makes sensing wafer presence, position, and other factors during processing more difficult
- Extreme thinness – being half as thick as silicon wafers (and trending thinner still) makes SiC wafers more difficult to retain during processing, as well as making them more prone to cracking and chipping
- Stress sensitivity – because of their thinness, SiC wafers are susceptible to stress, which can lead to bow and warp issues that must be addressed with advanced wafer handling technology and a flexible system architecture
Finding ways to overcome these challenges is vital, as CMP contributes significantly to improving the quality and performance of SiC wafers. Chief benefits currently imparted by CMP and their resulting outcomes are shown in the table.
CMP will continue evolving to meet the growing demands of SiC wafer production, beyond ongoing advancements in hardware technology. Many improvements will be made in CMP consumables for SIC processing, such as pads and slurries. Currently at a relatively immature state, these products have very different characteristics and property requirements compared to conventional CMP consumables.
Considerable effort is also being put toward reducing manufacturing costs for SiC wafers, as this will enable further market demand and new applications for SiC-based devices. As new advancements keep reducing CoO for SiC production, the total available market for SiC-based devices will continue to increase accordingly.
The role we play
Axus Technology is highly focused on developing and bringing to market novel, differentiated technologies specifically for SiC CMP. In 2020, recognizing the need for a new approach to CMP technology, we brought to market our Capstone platform, specifically designed to deliver high throughput and other capabilities optimized for SiC and other compound semiconductors.
Over the years, we have continually refined and improved the Capstone system, adding unique features that both refine and expand its capabilities, including:
- Integrated wafer flipping for double-sided polishing to manage wafer stress
- Process Temperature Control, enabling higher pressures, speeds, removal rates and throughput
- Dual wafer size processing, enabling two different wafer sizes to run simultaneously
- Integrated slurry reclaim, providing substantial CoO reduction and environmental quality
- Fulcrum carriers for improved flatness for flatted wafers
- Crystal carriers for fragile wafer handling and processing
- Improved wafer cleaning system with the integrated Aquarius to ensure excellent post processing defect levels.
Since introducing Capstone and its supporting products and technologies, we’ve been at the forefront of SiC CMP. As SiC device makers increasingly realize the benefits of single-wafer processing compared to batch – including better process control, lower cost of ownership, and higher throughput – we have been leading the transition from low-end batch polishing methods and tools to the industry’s most advanced 200mm single-wafer CMP tools. Moreover, we’re well positioned to continue on this trajectory.
Thanks to our leading market share position in SiC CMP and the significant investment and resources associated with our CMP foundry, Axus Technology enjoys ongoing close and collaborative engagement with essentially all top-tier suppliers of SiC CMP consumables. As many of the anticipated near-term improvements in SiC process improvements and cost-reduction efforts will likely evolve from consumable improvements, these engagements will continue to advance SiC market adoption along with the aforementioned cost improvements.
Continuing hardware-related technology improvements such as those mentioned above help further advancements that come with continuous testing, learning and innovation, such as those present in our SiC CMP technology roadmap. With our deep understanding of machine architecture, SiC material, and processing knowledge and innovation agility, Axus Technology is well positioned to lead CMP for SiC and other compound semiconductors into the future.
